1. Field of the Invention
The present invention generally relates to a method for manufacturing a semiconductor package having electrodes penetrating through a semiconductor wafer.
2. Description of the Related Art
A package for mounting a semiconductor chip (hereinafter referred to as “semiconductor package”) has an electrode (penetration electrode) penetrating therethrough for electrically connecting a semiconductor chip and a substrate. Conventional examples are shown in Japanese Laid-Open Patent Application Nos. 2003-31719 and 10-223833.
In recent years, as the heat releasing values increases along with the increase in energy consumption of an MPU (Micro Processing Unit), and as the number of pins serving as external connecting terminals increases, there is a greater demand in employing a material having little thermal expansion and being able to be micro fabricated, as a material for the semiconductor package. In response to such demand, a semiconductor such as silicon is proposed as the material for the semiconductor package.
FIGS. 1 through 9 are cross-sectional views illustrating a conventional process (method) for manufacturing a semiconductor package. In a first process shown in FIG. 1, resist 520 having holes 522 is formed on a top surface of a silicon wafer 510. Next, in a second process shown in FIG. 2, holes 512 are formed by dry etching in portions of the silicon wafer 510 exposed where the holes 522 of the resist 520 are situated. Next, in a third process shown in FIG. 3, the resist 520 formed on the top surface of the silicon wafer 510 is removed.
In a fourth process shown in FIG. 4, an insulating layer 530 is formed by a thermal oxidation method or a CVD (Chemical Vapor Deposition) method on the surface of the silicon wafer 510 (including inner wall portions of the holes 512). It is to be noted that the insulating layer 530 is not always required to be formed at the bottom surface of the silicon wafer 510. Next, in a fifth process shown in FIG. 5, a seed layer 540, which is required during a plating process, is formed by a CVD method or a sputtering method on the top surface of the insulating layer 530 formed on the top surface of the silicon wafer 510 and the holes 512. Next, in a sixth process as shown in FIG. 6, the inner portions of the holes 512 are filled with conductors by plating, to thereby obtain electrodes 550. In a seventh process shown in FIG. 7, exposed portions of the seed layer 540 are detached (separated).
Next, in an eighth process shown in FIG. 8, a thin-filming process (thin-filming) is performed on the silicon wafer 510, thereby exposing the electrodes 550 at the bottom surface of the silicon wafer 510. More specifically, in performing the thin-filming process on the silicon wafer 510, first, the bottom surface of the silicon wafer 510 is polished with, for example, a grind stone; then, the silicon wafer 510 is removed by a wet etching method until reaching a state immediately before the electrodes 550 become exposed; and then, finally, the bottom surface of the silicon wafer 510 is polished with, for example, a cloth containing a polishing agent, thereby exposing the electrodes 550 at the bottom surface of the silicon wafer 510.
Next, in a ninth process as shown in FIG. 9, an insulating layer 560 is formed on the bottom surface of the silicon wafer 510 in a manner exposing the electrodes 550. Accordingly, the electrodes (penetration electrodes) 550, penetrating the silicon wafer 510 from its top to bottom surface, are obtained for enabling a top portion thereof to be electrically connected to a semiconductor chip, and a bottom portion thereof to be electrically connected to a mounting substrate.
However, in the above-described conventional method, residue from the conductor, that is the material of the electrodes 550, may adhere to the bottom surface of the silicon wafer 510 during the eighth process (FIG. 8) where the bottom surface of the silicon wafer 510 is polished with the cloth containing a polishing agent. This may lead to shorting between the electrodes 550. Furthermore, in the ninth process (FIG. 9), forming the insulating layer 560 in a manner exposing the electrodes 550 is difficult since the electrodes 550 have extremely small diameters, for example, approximately 15 μm.